The present invention relates to an image display control system for displaying image data stored in a plurality of image memories having planes on a display device, the image display control system having a plurality of display controllers for controlling plane groups, each of which includes one or more planes.
One example of the conventional display control system is shown in FIG. 1.
In FIG. 1, reference numeral 1 designates an image bus for data transfer between a display control LSI 20 and a computer system body (not shown). An image memory 30 is connected to the display control LSI 20. Numeral 4 designates a color look-up table by which values read from the individual planes of the image memory 30 corresponding to each pixel are converted into a color for that pixel. The result of a search of the table 4 for the values for each pixel is output to a display device 5. In the present example, the image memory 30 is constructed by a dual-port image memory.
The display control LSI 20 includes an image bus interface (I/F) unit 100 for controlling an interface relative to the image bus 1, a display device control unit 102 for controlling the display device 5, a refresh activation unit 105 for periodically activating the refreshment of the dual-port image memory 30 in order to preserve the storage contents of the dual-port image memory 30, and an image memory I/F unit 104 for mediating between a read transfer request 112 from the display device control unit 102 and a refresh request 114 from the refresh activation unit 105 to cause a cycle of the dual-port image memory 30. In the case where the image memory is constructed by an ordinary static or dynamic memory, the read transfer request 112 is replaced by a data read request.
The display device control unit 102 generates a horizontal sync signal 120, a vertical sync signal 121 and a display period signal 122 which make the control of the display device 5. The controller 102 further generates the read transfer request 112 and serial clocks.
The display control LSI 20 receives a clock signal 6 (hereinafter referred to as a display clock signal) which provides the basis for the timing of control of the display device 5 and a clock signal 7 (hereinafter referred to as an image clock signal) which provides the basis of the timing of control of the dual-port image memory 30. A signal, from which the read transfer request 112 originates, is generated on the basis of the display clock signal 6. However, it is required that the read transfer request 112 is synchronous with a clock signal for operating the image memory I/F unit 104 (or the image clock signal 7). Therefore, in the case where the display clock signal 6 and the image clock signal 7 are asynchronous, the signal, from which the read transfer request 112 originates, is synchronized with the image clock signal 7 in the display device control unit 102.
As an example of a display control system, in which a display control including the above-mentioned signal synchronization is made having an asynchronous display clock signal and image clock signal, one can refer to JP-A-63-148292 which discloses an image memory access system.
The above conventional display control system fills its function with no problem in the case where the system has only one display control LSI. However, this prior art reference does not cope with the case where the system has a plurality of display control LSI's which should be operated in synchronism with each other to produce data to be simultaneously displayed on one display device. Especially, in the case where display and image clock signals are asynchronous, there is a problem that since the synchronization is independently made in each display control LSI, the timing of a signal after synchronization deviates between the display control LSI's to be provided corresponding to plane groups each of which includes one or more planes.
If it is possible to provide a display control system which has a plurality of display control LSI's for individual plane groups and makes it possible to synchronize the display control LSI's with each other to produce data to be simultaneously displayed on one display device even in the case where a display clock signal and an image clock signal are asynchronous, an increase in display colors by increasing the number of bits forming one pixel can be achieved by merely increasing the number of planes and the addition of a display control LSI('s) which controls the added plane(s).
In such a case, if the display control LSI to be added can be provided with the same construction as the display control LSI's having already possessed by the system, the efficiency of fabrication can be improved since the fabrication of one kind of LSI suffices.